Field effect transistors (FETs) are widely used in integrated chips. FETs comprise a source region, a drain region, and a gate electrode. By applying a bias voltage to the gate electrode, current flow between the source region and the drain region can be controlled. The sub-threshold drain current of a FET is the current that flows between the source region and the drain region of a FET when the transistor is in a sub-threshold region (i.e., for gate-to-source voltages below the threshold voltage). A large sub-threshold slope (i.e., a small sub-threshold swing) is typically desired since it improves the ratio between on and off currents, and therefore reduces leakage currents.